esp_usb.cpp

#include "esp_usb.hpp"
 
#if SOC_USB_OTG_SUPPORTED && defined(CONFIG_IDF_TARGET_ESP32S3) && \
    CONFIG_IDF_TARGET_ESP32S3
 
#include <algorithm>
#include <cstring>
 
#include "esp_err.h"
#include "esp_heap_caps.h"
#include "esp_memory_utils.h"
#include "hal/cache_hal.h"
 
namespace LibXR::ESPUSBDetail
{
 
#if SOC_CACHE_INTERNAL_MEM_VIA_L1CACHE || SOC_PSRAM_DMA_CAPABLE
extern "C" esp_err_t esp_cache_msync(void* addr, size_t size, int flags);
 
constexpr int kCacheSyncFlagUnaligned = (1 << 1);
constexpr int kCacheSyncFlagDirC2M = (1 << 2);
constexpr int kCacheSyncFlagDirM2C = (1 << 3);
 
bool CacheSyncDmaBuffer(const void* addr, size_t size, bool cache_to_mem,
                        bool allow_unaligned)
{
  if ((addr == nullptr) || (size == 0U))
  {
    return true;
  }
 
  uint32_t cache_level = 0;
  uint32_t cache_id = 0;
  const bool cache_supported = cache_hal_vaddr_to_cache_level_id(
      static_cast<uint32_t>(reinterpret_cast<uintptr_t>(addr)), size, &cache_level,
      &cache_id);
  if (!cache_supported)
  {
    return true;
  }
 
  int flags = cache_to_mem ? kCacheSyncFlagDirC2M : kCacheSyncFlagDirM2C;
  if (allow_unaligned && cache_to_mem)
  {
    flags |= kCacheSyncFlagUnaligned;
  }
  return esp_cache_msync(const_cast<void*>(addr), size, flags) == ESP_OK;
}
#else
bool CacheSyncDmaBuffer(const void*, size_t, bool, bool) { return true; }
#endif
 
size_t AlignUp(size_t value, size_t align)
{
  if (align <= 1U)
  {
    return value;
  }
  return ((value + align - 1U) / align) * align;
}
 
esp_dma_mem_info_t UsbDmaMemInfo()
{
  esp_dma_mem_info_t info = {};
  info.extra_heap_caps = MALLOC_CAP_INTERNAL;
  info.dma_alignment_bytes = kWordSize;
  return info;
}
 
bool CanUseDirectInDmaBuffer(const void* ptr, size_t size)
{
  if ((ptr == nullptr) || (size == 0U))
  {
    return size == 0U;
  }
 
  auto* start = static_cast<const uint8_t*>(ptr);
  auto* end = start + size - 1U;
  return esp_ptr_dma_capable(start) && esp_ptr_dma_capable(end) &&
         esp_ptr_word_aligned(ptr);
}
 
bool CanUseDirectOutDmaBuffer(const void* ptr, size_t size)
{
  if ((ptr == nullptr) || (size == 0U))
  {
    return false;
  }
 
  auto* start = static_cast<const uint8_t*>(ptr);
  auto* end = start + size - 1U;
  if (!esp_ptr_dma_capable(start) || !esp_ptr_dma_capable(end) ||
      !esp_ptr_word_aligned(ptr) ||
      !esp_dma_is_buffer_alignment_satisfied(ptr, size, UsbDmaMemInfo()))
  {
    return false;
  }
 
  uint32_t cache_level = 0;
  uint32_t cache_id = 0;
  const bool cache_supported = cache_hal_vaddr_to_cache_level_id(
      static_cast<uint32_t>(reinterpret_cast<uintptr_t>(ptr)), size, &cache_level,
      &cache_id);
  if (!cache_supported)
  {
    return true;
  }
 
  const uintptr_t addr = reinterpret_cast<uintptr_t>(ptr);
  return ((addr % kUsbDmaAlignment) == 0U) && (AlignUp(size, kUsbDmaAlignment) == size);
}
 
uint16_t CalcRxFifoWords(uint16_t largest_packet_size, uint8_t ep_count)
{
  return static_cast<uint16_t>(13U + 1U + 2U * (((largest_packet_size + 3U) / 4U) + 1U) +
                               2U * ep_count);
}
 
uint16_t CalcConfiguredRxFifoWords(uint16_t largest_packet_size, uint8_t ep_count,
                                   bool dma_enabled)
{
  uint16_t words = CalcRxFifoWords(largest_packet_size, ep_count);
  if (dma_enabled)
  {
    words = std::max<uint16_t>(words, kEsp32SxFsDmaMinRxFifoWords);
  }
  return words;
}
 
uint16_t GetHardwareFifoDepthWords()
{
  auto* dev = reinterpret_cast<usb_dwc_dev_t*>(kDwc2FsRegBase);
  return static_cast<uint16_t>(dev->ghwcfg3_reg.dfifodepth);
}
 
uint8_t EncodeEp0Mps(uint16_t packet_size)
{
  switch (packet_size)
  {
    case 8:
      return 3U;
    case 16:
      return 2U;
    case 32:
      return 1U;
    case 64:
    default:
      return 0U;
  }
}
 
uint16_t ClampPacketSize(LibXR::USB::Endpoint::Type type, uint16_t requested)
{
  switch (type)
  {
    case LibXR::USB::Endpoint::Type::CONTROL:
      return static_cast<uint16_t>(std::min<uint16_t>(requested, 64U));
    case LibXR::USB::Endpoint::Type::BULK:
      return static_cast<uint16_t>(std::min<uint16_t>(requested, 64U));
    case LibXR::USB::Endpoint::Type::INTERRUPT:
      return static_cast<uint16_t>(std::min<uint16_t>(requested, 64U));
    case LibXR::USB::Endpoint::Type::ISOCHRONOUS:
      return static_cast<uint16_t>(std::min<uint16_t>(requested, 1023U));
    default:
      return requested;
  }
}
 
uint16_t CalcTxFifoWords(uint16_t packet_size, bool dma_enabled)
{
  uint16_t words = static_cast<uint16_t>((packet_size + 3U) / 4U);
  if (dma_enabled)
  {
    words = std::max<uint16_t>(words, kEsp32SxFsMinTxFifoWords);
  }
  return words;
}
 
volatile uint32_t* GetEndpointFifo(usb_dwc_dev_t* dev, uint8_t ep_num)
{
  uintptr_t base = reinterpret_cast<uintptr_t>(dev);
  return reinterpret_cast<volatile uint32_t*>(
      base + kFifoBaseOffset + static_cast<uintptr_t>(ep_num) * kFifoStride);
}
 
void WriteFifoPacket(volatile uint32_t* fifo, const uint8_t* src, size_t size)
{
  for (size_t offset = 0; offset < size; offset += kWordSize)
  {
    uint32_t word = 0U;
    const size_t chunk = std::min(kWordSize, size - offset);
    std::memcpy(&word, src + offset, chunk);
    fifo[0] = word;
  }
}
 
void ReadFifoPacket(const volatile uint32_t* fifo, uint8_t* dst, size_t size)
{
  for (size_t offset = 0; offset < size; offset += kWordSize)
  {
    const uint32_t word = fifo[0];
    const size_t chunk = std::min(kWordSize, size - offset);
    std::memcpy(dst + offset, &word, chunk);
  }
}
 
uint16_t PacketCount(size_t size, uint16_t max_packet_size)
{
  if (size == 0U)
  {
    return 1U;
  }
  return static_cast<uint16_t>((size + max_packet_size - 1U) / max_packet_size);
}
 
void FlushTxFifo(usb_dwc_dev_t* dev, uint8_t fifo_num)
{
  dev->grstctl_reg.txfnum = fifo_num;
  dev->grstctl_reg.txfflsh = 1;
  while (dev->grstctl_reg.txfflsh)
  {
  }
}
 
void DisableInEndpointAndWait(usb_dwc_dev_t* dev)
{
  auto& ctl = dev->diepctl0_reg;
  auto& intr = dev->diepint0_reg;
  if (!ctl.epena)
  {
    return;
  }
 
  ctl.snak = 1;
  while (!intr.inepnakeff)
  {
  }
 
  usb_dwc_diepint0_reg_t clear_nak = {};
  clear_nak.inepnakeff = 1;
  intr.val = clear_nak.val;
 
  ctl.epdis = 1;
  while (!intr.epdisbld)
  {
  }
 
  usb_dwc_diepint0_reg_t clear_dis = {};
  clear_dis.epdisbld = 1;
  intr.val = clear_dis.val;
  FlushTxFifo(dev, 0U);
}
 
void DisableInEndpointAndWait(usb_dwc_dev_t* dev, uint8_t ep_num)
{
  auto& ctl = dev->in_eps[ep_num - 1U].diepctl_reg;
  auto& intr = dev->in_eps[ep_num - 1U].diepint_reg;
  if (!ctl.epena)
  {
    return;
  }
 
  ctl.snak = 1;
  while (!intr.inepnakeff)
  {
  }
 
  usb_dwc_diepint_reg_t clear_nak = {};
  clear_nak.inepnakeff = 1;
  intr.val = clear_nak.val;
 
  ctl.epdis = 1;
  while (!intr.epdisbld)
  {
  }
 
  usb_dwc_diepint_reg_t clear_dis = {};
  clear_dis.epdisbld = 1;
  intr.val = clear_dis.val;
  FlushTxFifo(dev, ep_num);
}
 
}  // namespace LibXR::ESPUSBDetail
 
#endif