83{
84 if (tim == TIM1) RCC_APB2PeriphClockCmd(RCC_APB2Periph_TIM1, ENABLE);
85#if defined(TIM8) && defined(RCC_APB2Periph_TIM8)
86 else if (tim == TIM8)
87 RCC_APB2PeriphClockCmd(RCC_APB2Periph_TIM8, ENABLE);
88#endif
89#if defined(TIM9) && defined(RCC_APB2Periph_TIM9)
90 else if (tim == TIM9)
91 RCC_APB2PeriphClockCmd(RCC_APB2Periph_TIM9, ENABLE);
92#endif
93#if defined(TIM10) && defined(RCC_APB2Periph_TIM10)
94 else if (tim == TIM10)
95 RCC_APB2PeriphClockCmd(RCC_APB2Periph_TIM10, ENABLE);
96#endif
97#if defined(TIM2) && defined(RCC_APB1Periph_TIM2)
98 else if (tim == TIM2)
99 RCC_APB1PeriphClockCmd(RCC_APB1Periph_TIM2, ENABLE);
100#endif
101#if defined(TIM3) && defined(RCC_APB1Periph_TIM3)
102 else if (tim == TIM3)
103 RCC_APB1PeriphClockCmd(RCC_APB1Periph_TIM3, ENABLE);
104#endif
105#if defined(TIM4) && defined(RCC_APB1Periph_TIM4)
106 else if (tim == TIM4)
107 RCC_APB1PeriphClockCmd(RCC_APB1Periph_TIM4, ENABLE);
108#endif
109#if defined(TIM5) && defined(RCC_APB1Periph_TIM5)
110 else if (tim == TIM5)
111 RCC_APB1PeriphClockCmd(RCC_APB1Periph_TIM5, ENABLE);
112#endif
113#if defined(TIM6) && defined(RCC_APB1Periph_TIM6)
114 else if (tim == TIM6)
115 RCC_APB1PeriphClockCmd(RCC_APB1Periph_TIM6, ENABLE);
116#endif
117#if defined(TIM7) && defined(RCC_APB1Periph_TIM7)
118 else if (tim == TIM7)
119 RCC_APB1PeriphClockCmd(RCC_APB1Periph_TIM7, ENABLE);
120#endif
121#if defined(TIM12) && defined(RCC_APB1Periph_TIM12)
122 else if (tim == TIM12)
123 RCC_APB1PeriphClockCmd(RCC_APB1Periph_TIM12, ENABLE);
124#endif
125#if defined(TIM13) && defined(RCC_APB1Periph_TIM13)
126 else if (tim == TIM13)
127 RCC_APB1PeriphClockCmd(RCC_APB1Periph_TIM13, ENABLE);
128#endif
129#if defined(TIM14) && defined(RCC_APB1Periph_TIM14)
130 else if (tim == TIM14)
131 RCC_APB1PeriphClockCmd(RCC_APB1Periph_TIM14, ENABLE);
132#endif
133}