libxr  1.0
Want to be the best embedded framework
Loading...
Searching...
No Matches
ch32_uart.cpp
1// NOLINTBEGIN(cppcoreguidelines-pro-type-cstyle-cast,performance-no-int-to-ptr)
2// ch32_uart.cpp
3
4#include "ch32_uart.hpp"
5
6#include "ch32_dma.hpp"
7#include "ch32_gpio.hpp"
8
9using namespace LibXR;
10
11// Static instance map.
12CH32UART* CH32UART::map_[ch32_uart_id_t::CH32_UART_NUMBER] = {nullptr};
13
14// Constructor: USART, DMA, and GPIO initialization.
15CH32UART::CH32UART(ch32_uart_id_t id, RawData dma_rx, RawData dma_tx,
16 GPIO_TypeDef* tx_gpio_port, uint16_t tx_gpio_pin,
17 GPIO_TypeDef* rx_gpio_port, uint16_t rx_gpio_pin, uint32_t pin_remap,
18 uint32_t tx_queue_size, UART::Configuration config)
19 : UART(&_read_port, &_write_port),
20 id_(id),
21 _read_port(dma_rx.size_),
22 _write_port(tx_queue_size, dma_tx.size_ / 2),
23 dma_buff_rx_(dma_rx),
24 dma_buff_tx_(dma_tx),
25 instance_(ch32_uart_get_instance_id(id)),
26 dma_rx_channel_(CH32_UART_RX_DMA_CHANNEL_MAP[id]),
27 dma_tx_channel_(CH32_UART_TX_DMA_CHANNEL_MAP[id])
28{
29 map_[id] = this;
30
31 bool tx_enable = dma_tx.size_ > 1;
32 bool rx_enable = dma_rx.size_ > 0;
33
34 ASSERT(tx_enable || rx_enable);
35 if (tx_enable)
36 {
37 ASSERT(dma_tx_channel_ != nullptr);
38 ASSERT(CH32_UART_TX_DMA_IT_MAP[id] != 0);
39 }
40 if (rx_enable)
41 {
42 ASSERT(dma_rx_channel_ != nullptr);
43 ASSERT(CH32_UART_RX_DMA_IT_TC_MAP[id] != 0);
44 ASSERT(CH32_UART_RX_DMA_IT_HT_MAP[id] != 0);
45 }
46
47 /* GPIO配置(TX: 推挽输出,RX: 悬空输入) */
48 GPIO_InitTypeDef gpio_init = {};
49 gpio_init.GPIO_Speed = GPIO_Speed_50MHz;
50
51 if (tx_enable)
52 {
53 RCC_APB2PeriphClockCmd(ch32_get_gpio_periph(tx_gpio_port), ENABLE);
54 gpio_init.GPIO_Pin = tx_gpio_pin;
55 gpio_init.GPIO_Mode = GPIO_Mode_AF_PP;
56 GPIO_Init(tx_gpio_port, &gpio_init);
57 (*write_port_) = WriteFun;
58 }
59
60 if (rx_enable)
61 {
62 RCC_APB2PeriphClockCmd(ch32_get_gpio_periph(rx_gpio_port), ENABLE);
63 gpio_init.GPIO_Pin = rx_gpio_pin;
64 gpio_init.GPIO_Mode = GPIO_Mode_IN_FLOATING;
65 GPIO_Init(rx_gpio_port, &gpio_init);
66 (*read_port_) = ReadFun;
67 }
68
69 /* 可选:引脚重映射 */
70 if (pin_remap != 0)
71 {
72 RCC_APB2PeriphClockCmd(RCC_APB2Periph_AFIO, ENABLE);
73 GPIO_PinRemapConfig(pin_remap, ENABLE);
74 }
75
76 /* 串口外设时钟使能 */
77 if (CH32_UART_APB_MAP[id] == 1)
78 {
79 RCC_APB1PeriphClockCmd(CH32_UART_RCC_PERIPH_MAP[id], ENABLE);
80 }
81 else if (CH32_UART_APB_MAP[id] == 2)
82 {
83 RCC_APB2PeriphClockCmd(CH32_UART_RCC_PERIPH_MAP[id], ENABLE);
84 }
85 else
86 {
87 ASSERT(false);
88 }
89 RCC_AHBPeriphClockCmd(CH32_UART_RCC_PERIPH_MAP_DMA[id], ENABLE);
90
91 // 3. USART 配置
92 USART_InitTypeDef usart_cfg = {};
93 usart_cfg.USART_BaudRate = config.baudrate;
94 usart_cfg.USART_StopBits =
95 (config.stop_bits == 2) ? USART_StopBits_2 : USART_StopBits_1;
96 switch (config.parity)
97 {
99 usart_cfg.USART_Parity = USART_Parity_No;
100 usart_cfg.USART_WordLength = USART_WordLength_8b;
101 break;
103 usart_cfg.USART_Parity = USART_Parity_Even;
104 usart_cfg.USART_WordLength = USART_WordLength_9b;
105 break;
107 usart_cfg.USART_Parity = USART_Parity_Odd;
108 usart_cfg.USART_WordLength = USART_WordLength_9b;
109 break;
110 default:
111 ASSERT(false);
112 }
113
114 usart_cfg.USART_HardwareFlowControl = USART_HardwareFlowControl_None;
115 usart_cfg.USART_Mode =
116 (tx_enable ? USART_Mode_Tx : 0) | (rx_enable ? USART_Mode_Rx : 0);
117 uart_mode_ = usart_cfg.USART_Mode;
118 USART_Init(instance_, &usart_cfg);
119
120 /* DMA 配置 */
121 DMA_InitTypeDef dma_init = {};
122 dma_init.DMA_PeripheralInc = DMA_PeripheralInc_Disable;
123 dma_init.DMA_MemoryInc = DMA_MemoryInc_Enable;
124 dma_init.DMA_PeripheralDataSize = DMA_PeripheralDataSize_Byte;
125 dma_init.DMA_MemoryDataSize = DMA_MemoryDataSize_Byte;
126 dma_init.DMA_Priority = DMA_Priority_High;
127 dma_init.DMA_M2M = DMA_M2M_Disable;
128
129 if (rx_enable)
130 {
131 ch32_dma_callback_t rx_cb_fun = [](void* arg)
132 { reinterpret_cast<CH32UART*>(arg)->RxDmaIRQHandler(); };
133
134 ch32_dma_register_callback(ch32_dma_get_id(CH32_UART_RX_DMA_CHANNEL_MAP[id]),
135 rx_cb_fun, this);
136
137 DMA_DeInit(dma_rx_channel_);
138 dma_init.DMA_PeripheralBaseAddr = (uint32_t)&instance_->DATAR;
139 dma_init.DMA_MemoryBaseAddr = (uint32_t)dma_buff_rx_.addr_;
140 dma_init.DMA_DIR = DMA_DIR_PeripheralSRC;
141 dma_init.DMA_Mode = DMA_Mode_Circular;
142 dma_init.DMA_BufferSize = dma_buff_rx_.size_;
143 DMA_Init(dma_rx_channel_, &dma_init);
144 DMA_Cmd(dma_rx_channel_, ENABLE);
145 DMA_ITConfig(dma_rx_channel_, DMA_IT_TC, ENABLE);
146 DMA_ITConfig(dma_rx_channel_, DMA_IT_HT, ENABLE);
147 USART_DMACmd(instance_, USART_DMAReq_Rx, ENABLE);
148 }
149
150 if (tx_enable)
151 {
152 ch32_dma_callback_t tx_cb_fun = [](void* arg)
153 { reinterpret_cast<CH32UART*>(arg)->TxDmaIRQHandler(); };
154
155 ch32_dma_register_callback(ch32_dma_get_id(CH32_UART_TX_DMA_CHANNEL_MAP[id]),
156 tx_cb_fun, this);
157 DMA_DeInit(dma_tx_channel_);
158 dma_init.DMA_PeripheralBaseAddr = (u32)(&instance_->DATAR);
159 dma_init.DMA_MemoryBaseAddr = 0;
160 dma_init.DMA_DIR = DMA_DIR_PeripheralDST;
161 dma_init.DMA_Mode = DMA_Mode_Normal;
162 dma_init.DMA_BufferSize = 0;
163 DMA_Init(dma_tx_channel_, &dma_init);
164 DMA_ITConfig(dma_tx_channel_, DMA_IT_TC, ENABLE);
165 USART_DMACmd(instance_, USART_DMAReq_Tx, ENABLE);
166 }
167
168 // 6. USART和相关中断
169 USART_Cmd(instance_, ENABLE);
170
171 if (rx_enable)
172 {
173 USART_ITConfig(instance_, USART_IT_IDLE, ENABLE);
174 NVIC_EnableIRQ(CH32_DMA_IRQ_MAP[ch32_dma_get_id(dma_rx_channel_)]);
175 }
176
177 if (tx_enable)
178 {
179 NVIC_EnableIRQ(CH32_DMA_IRQ_MAP[ch32_dma_get_id(dma_tx_channel_)]);
180 }
181
182 NVIC_EnableIRQ(CH32_UART_IRQ_MAP[id]);
183}
184
185// Runtime USART configuration.
187{
188 USART_InitTypeDef usart_cfg = {};
189 usart_cfg.USART_BaudRate = config.baudrate;
190 usart_cfg.USART_StopBits =
191 (config.stop_bits == 2) ? USART_StopBits_2 : USART_StopBits_1;
192
193 switch (config.parity)
194 {
196 usart_cfg.USART_Parity = USART_Parity_No;
197 usart_cfg.USART_WordLength = USART_WordLength_8b;
198 break;
200 usart_cfg.USART_Parity = USART_Parity_Even;
201 usart_cfg.USART_WordLength = USART_WordLength_9b;
202 break;
204 usart_cfg.USART_Parity = USART_Parity_Odd;
205 usart_cfg.USART_WordLength = USART_WordLength_9b;
206 break;
207 default:
208 return ErrorCode::NOT_SUPPORT;
209 }
210
211 usart_cfg.USART_Mode = uart_mode_;
212 usart_cfg.USART_HardwareFlowControl = USART_HardwareFlowControl_None;
213 USART_DeInit(instance_);
214 USART_Init(instance_, &usart_cfg);
215
216 if (uart_mode_ & USART_Mode_Rx)
217 {
218 USART_DMACmd(instance_, USART_DMAReq_Rx, ENABLE);
219 USART_ITConfig(instance_, USART_IT_IDLE, ENABLE);
220 }
221
222 if (uart_mode_ & USART_Mode_Tx)
223 {
224 USART_DMACmd(instance_, USART_DMAReq_Tx, ENABLE);
225 }
226
227 USART_Cmd(instance_, ENABLE);
228
229 if (tx_busy_.IsSet())
230 {
231 dma_tx_channel_->CNTR = dma_buff_tx_.GetActiveLength();
232 dma_tx_channel_->MADDR = reinterpret_cast<uint32_t>(dma_buff_tx_.ActiveBuffer());
233 DMA_Cmd(dma_tx_channel_, ENABLE);
234 }
235
236 return ErrorCode::OK;
237}
238
239// Write callback (DMA-based transfer).
240ErrorCode CH32UART::WriteFun(WritePort& port, bool)
241{
242 CH32UART* uart = CONTAINER_OF(&port, CH32UART, _write_port);
243
244 if (uart->in_tx_isr.IsSet())
245 {
246 return ErrorCode::PENDING;
247 }
248
249 if (!uart->dma_buff_tx_.HasPending())
250 {
251 WriteInfoBlock info;
252 if (port.queue_info_->Peek(info) != ErrorCode::OK)
253 {
254 return ErrorCode::PENDING;
255 }
256
257 uint8_t* buffer = nullptr;
258 bool use_pending = false;
259
260 // DMA空闲判断
261 bool dma_ready = uart->dma_tx_channel_->CNTR == 0;
262 if (dma_ready)
263 {
264 buffer = reinterpret_cast<uint8_t*>(uart->dma_buff_tx_.ActiveBuffer());
265 }
266 else
267 {
268 buffer = reinterpret_cast<uint8_t*>(uart->dma_buff_tx_.PendingBuffer());
269 use_pending = true;
270 }
271
272 if (port.queue_data_->PopBatch(buffer, info.data.size_) != ErrorCode::OK)
273 {
274 ASSERT(false);
275 return ErrorCode::EMPTY;
276 }
277
278 if (use_pending)
279 {
280 uart->dma_buff_tx_.SetPendingLength(info.data.size_);
281 uart->dma_buff_tx_.EnablePending();
282 // 检查当前DMA是否可切换
283 bool dma_ready = uart->dma_tx_channel_->CNTR == 0;
284 if (dma_ready && uart->dma_buff_tx_.HasPending())
285 {
286 uart->dma_buff_tx_.Switch();
287 }
288 else
289 {
290 return ErrorCode::PENDING;
291 }
292 }
293
294 port.queue_info_->Pop(uart->write_info_active_);
295
296 DMA_Cmd(uart->dma_tx_channel_, DISABLE);
297 uart->dma_tx_channel_->MADDR =
298 reinterpret_cast<uint32_t>(uart->dma_buff_tx_.ActiveBuffer());
299 uart->dma_tx_channel_->CNTR = info.data.size_;
300 uart->dma_buff_tx_.SetActiveLength(info.data.size_);
301 uart->tx_busy_.Set();
302 DMA_Cmd(uart->dma_tx_channel_, ENABLE);
303
304 return ErrorCode::OK;
305 }
306 return ErrorCode::PENDING;
307}
308
309// Read callback (interrupt-driven).
310ErrorCode CH32UART::ReadFun(ReadPort&, bool)
311{
312 // 接收由 IDLE 中断驱动,读取在 ISR 中完成
313 return ErrorCode::PENDING;
314}
315
316void ch32_uart_rx_isr_handler(LibXR::CH32UART* uart)
317{
318 auto rx_buf = static_cast<uint8_t*>(uart->dma_buff_rx_.addr_);
319 size_t dma_size = uart->dma_buff_rx_.size_;
320 size_t curr_pos = dma_size - uart->dma_rx_channel_->CNTR;
321 size_t last_pos = uart->last_rx_pos_;
322
323 if (curr_pos != last_pos)
324 {
325 if (curr_pos > last_pos)
326 {
327 // 普通区间
328 uart->_read_port.queue_data_->PushBatch(&rx_buf[last_pos], curr_pos - last_pos);
329 }
330 else
331 {
332 // 回卷区
333 uart->_read_port.queue_data_->PushBatch(&rx_buf[last_pos], dma_size - last_pos);
334 uart->_read_port.queue_data_->PushBatch(&rx_buf[0], curr_pos);
335 }
336 uart->last_rx_pos_ = curr_pos;
337 uart->_read_port.ProcessPendingReads(true);
338 }
339}
340
341// USART IDLE interrupt handler.
342extern "C" void ch32_uart_isr_handler_idle(ch32_uart_id_t id)
343{
344 auto uart = CH32UART::map_[id];
345 if (!uart)
346 {
347 return;
348 }
349
350 // 检查和清除IDLE标志
351 if (!USART_GetITStatus(uart->instance_, USART_IT_IDLE))
352 {
353 return;
354 }
355
356 USART_ReceiveData(uart->instance_);
357
358 ch32_uart_rx_isr_handler(uart);
359}
360
361// DMA TX completion interrupt handler.
362extern "C" void ch32_uart_isr_handler_tx_cplt(CH32UART* uart)
363{
364 DMA_ClearITPendingBit(CH32_UART_TX_DMA_IT_MAP[uart->id_]);
365
366 uart->tx_busy_.Clear();
367
368 Flag::ScopedRestore tx_flag(uart->in_tx_isr);
369
370 size_t pending_len = uart->dma_buff_tx_.GetPendingLength();
371
372 if (pending_len == 0)
373 {
374 return;
375 }
376
377 uart->dma_buff_tx_.Switch();
378
379 auto* buf = reinterpret_cast<uint8_t*>(uart->dma_buff_tx_.ActiveBuffer());
380 DMA_Cmd(uart->dma_tx_channel_, DISABLE);
381 uart->dma_tx_channel_->MADDR = (uint32_t)buf;
382 uart->dma_tx_channel_->CNTR = pending_len;
383 uart->dma_buff_tx_.SetActiveLength(pending_len);
384 DMA_Cmd(uart->dma_tx_channel_, ENABLE);
385
386 WriteInfoBlock& current_info = uart->write_info_active_;
387
388 // 有pending包,继续取下一包
389 if (uart->_write_port.queue_info_->Pop(current_info) != ErrorCode::OK)
390 {
391 ASSERT(false);
392 return;
393 }
394
395 uart->write_port_->Finish(true, ErrorCode::OK, current_info);
396
397 // 预装pending区
398 WriteInfoBlock next_info;
399 if (uart->write_port_->queue_info_->Peek(next_info) != ErrorCode::OK)
400 {
401 return;
402 }
403
404 if (uart->write_port_->queue_data_->PopBatch(
405 reinterpret_cast<uint8_t*>(uart->dma_buff_tx_.PendingBuffer()),
406 next_info.data.size_) != ErrorCode::OK)
407 {
408 ASSERT(false);
409 return;
410 }
411
412 uart->dma_buff_tx_.SetPendingLength(next_info.data.size_);
413
414 uart->dma_buff_tx_.EnablePending();
415}
416
417// DMA channel IRQ callbacks.
418void CH32UART::TxDmaIRQHandler()
419{
420 if (DMA_GetITStatus(CH32_UART_TX_DMA_IT_MAP[id_]) == RESET)
421 {
422 return;
423 }
424
425 if (dma_tx_channel_->CNTR == 0)
426 {
427 ch32_uart_isr_handler_tx_cplt(this);
428 }
429}
430
440{
441 if (DMA_GetITStatus(CH32_UART_RX_DMA_IT_HT_MAP[id_]) == SET)
442 {
443 DMA_ClearITPendingBit(CH32_UART_RX_DMA_IT_HT_MAP[id_]);
444 ch32_uart_rx_isr_handler(this);
445 }
446
447 if (DMA_GetITStatus(CH32_UART_RX_DMA_IT_TC_MAP[id_]) == SET)
448 {
449 DMA_ClearITPendingBit(CH32_UART_RX_DMA_IT_TC_MAP[id_]);
450 ch32_uart_rx_isr_handler(this);
451 }
452}
453
454// USART IRQ entry adapters.
455#if defined(USART1)
456// NOLINTNEXTLINE(readability-identifier-naming)
457extern "C" void USART1_IRQHandler(void) __attribute__((interrupt));
458// NOLINTNEXTLINE(readability-identifier-naming)
459extern "C" void USART1_IRQHandler(void) { ch32_uart_isr_handler_idle(CH32_USART1); }
460#endif
461#if defined(USART2)
462// NOLINTNEXTLINE(readability-identifier-naming)
463extern "C" void USART2_IRQHandler(void) __attribute__((interrupt));
464// NOLINTNEXTLINE(readability-identifier-naming)
465extern "C" void USART2_IRQHandler(void) { ch32_uart_isr_handler_idle(CH32_USART2); }
466#endif
467#if defined(USART3)
468// NOLINTNEXTLINE(readability-identifier-naming)
469extern "C" void USART3_IRQHandler(void) __attribute__((interrupt));
470// NOLINTNEXTLINE(readability-identifier-naming)
471extern "C" void USART3_IRQHandler(void) { ch32_uart_isr_handler_idle(CH32_USART3); }
472#endif
473#if defined(USART4)
474// NOLINTNEXTLINE(readability-identifier-naming)
475extern "C" void USART4_IRQHandler(void) __attribute__((interrupt));
476// NOLINTNEXTLINE(readability-identifier-naming)
477extern "C" void USART4_IRQHandler(void) { ch32_uart_isr_handler_idle(CH32_USART4); }
478#endif
479#if defined(USART5)
480// NOLINTNEXTLINE(readability-identifier-naming)
481extern "C" void USART5_IRQHandler(void) __attribute__((interrupt));
482// NOLINTNEXTLINE(readability-identifier-naming)
483extern "C" void USART5_IRQHandler(void) { ch32_uart_isr_handler_idle(CH32_USART5); }
484#endif
485#if defined(USART6)
486// NOLINTNEXTLINE(readability-identifier-naming)
487extern "C" void USART6_IRQHandler(void) __attribute__((interrupt));
488// NOLINTNEXTLINE(readability-identifier-naming)
489extern "C" void USART6_IRQHandler(void) { ch32_uart_isr_handler_idle(CH32_USART6); }
490#endif
491#if defined(USART7)
492// NOLINTNEXTLINE(readability-identifier-naming)
493extern "C" void USART7_IRQHandler(void) __attribute__((interrupt));
494// NOLINTNEXTLINE(readability-identifier-naming)
495extern "C" void USART7_IRQHandler(void) { ch32_uart_isr_handler_idle(CH32_USART7); }
496#endif
497#if defined(USART8)
498// NOLINTNEXTLINE(readability-identifier-naming)
499extern "C" void USART8_IRQHandler(void) __attribute__((interrupt));
500// NOLINTNEXTLINE(readability-identifier-naming)
501extern "C" void USART8_IRQHandler(void) { ch32_uart_isr_handler_idle(CH32_USART8); }
502#endif
503#if defined(UART1)
504// NOLINTNEXTLINE(readability-identifier-naming)
505extern "C" void UART1_IRQHandler(void) __attribute__((interrupt));
506// NOLINTNEXTLINE(readability-identifier-naming)
507extern "C" void UART1_IRQHandler(void) { ch32_uart_isr_handler_idle(CH32_UART1); }
508#endif
509#if defined(UART2)
510// NOLINTNEXTLINE(readability-identifier-naming)
511extern "C" void UART2_IRQHandler(void) __attribute__((interrupt));
512// NOLINTNEXTLINE(readability-identifier-naming)
513extern "C" void UART2_IRQHandler(void) { ch32_uart_isr_handler_idle(CH32_UART2); }
514#endif
515#if defined(UART3)
516// NOLINTNEXTLINE(readability-identifier-naming)
517extern "C" void UART3_IRQHandler(void) __attribute__((interrupt));
518// NOLINTNEXTLINE(readability-identifier-naming)
519extern "C" void UART3_IRQHandler(void) { ch32_uart_isr_handler_idle(CH32_UART3); }
520#endif
521#if defined(UART4)
522// NOLINTNEXTLINE(readability-identifier-naming)
523extern "C" void UART4_IRQHandler(void) __attribute__((interrupt));
524// NOLINTNEXTLINE(readability-identifier-naming)
525extern "C" void UART4_IRQHandler(void) { ch32_uart_isr_handler_idle(CH32_UART4); }
526#endif
527#if defined(UART5)
528// NOLINTNEXTLINE(readability-identifier-naming)
529extern "C" void UART5_IRQHandler(void) __attribute__((interrupt));
530// NOLINTNEXTLINE(readability-identifier-naming)
531extern "C" void UART5_IRQHandler(void) { ch32_uart_isr_handler_idle(CH32_UART5); }
532#endif
533#if defined(UART6)
534// NOLINTNEXTLINE(readability-identifier-naming)
535extern "C" void UART6_IRQHandler(void) __attribute__((interrupt));
536// NOLINTNEXTLINE(readability-identifier-naming)
537extern "C" void UART6_IRQHandler(void) { ch32_uart_isr_handler_idle(CH32_UART6); }
538#endif
539#if defined(UART7)
540// NOLINTNEXTLINE(readability-identifier-naming)
541extern "C" void UART7_IRQHandler(void) __attribute__((interrupt));
542// NOLINTNEXTLINE(readability-identifier-naming)
543extern "C" void UART7_IRQHandler(void) { ch32_uart_isr_handler_idle(CH32_UART7); }
544#endif
545#if defined(UART8)
546// NOLINTNEXTLINE(readability-identifier-naming)
547extern "C" void UART8_IRQHandler(void) __attribute__((interrupt));
548// NOLINTNEXTLINE(readability-identifier-naming)
549extern "C" void UART8_IRQHandler(void) { ch32_uart_isr_handler_idle(CH32_UART8); }
550#endif
551
552// NOLINTEND(cppcoreguidelines-pro-type-cstyle-cast,performance-no-int-to-ptr)
CH32 UART 驱动实现 / CH32 UART driver implementation.
Definition ch32_uart.hpp:19
void RxDmaIRQHandler()
DMA中断处理函数
ErrorCode SetConfig(UART::Configuration config)
设置 UART 配置 / Sets the UART configuration
CH32UART(ch32_uart_id_t id, RawData dma_rx, RawData dma_tx, GPIO_TypeDef *tx_gpio_port, uint16_t tx_gpio_pin, GPIO_TypeDef *rx_gpio_port, uint16_t rx_gpio_pin, uint32_t pin_remap=0, uint32_t tx_queue_size=5, UART::Configuration config={115200, UART::Parity::NO_PARITY, 8, 1})
构造 UART 对象 / Construct UART object
Definition ch32_uart.cpp:15
size_t size_
数据大小(字节)。 The size of the data (in bytes).
void SetActiveLength(size_t length)
设置当前活动缓冲区的数据长度 Sets the size of the active buffer
void SetPendingLength(size_t length)
设置备用缓冲区的数据长度 Sets the size of the pending buffer
void EnablePending()
手动启用 pending 状态 Manually sets the pending state to true
bool HasPending() const
判断是否有待切换的缓冲区 Checks whether a pending buffer is ready
uint8_t * ActiveBuffer() const
获取当前正在使用的缓冲区指针 Returns the currently active buffer
size_t GetActiveLength() const
获取当前活动缓冲区中准备好的数据长度 Gets the size of valid data in active buffer
uint8_t * PendingBuffer() const
获取备用缓冲区的指针 Returns the pending (inactive) buffer
void Switch()
切换到备用缓冲区(若其有效) Switches to the pending buffer if it's valid
size_t GetPendingLength() const
获取 pending 缓冲区中准备好的数据长度 Gets the size of valid data in pending buffer
void Set() noexcept
置位标志 / Set the flag
Definition flag.hpp:125
bool IsSet() const noexcept
判断是否已置位 / Check whether the flag is set
Definition flag.hpp:138
void Clear() noexcept
清除标志 / Clear the flag
Definition flag.hpp:130
作用域标志管理器:构造时写入指定值,析构时恢复原值 / Scoped flag restorer: set on entry, restore on exit
Definition flag.hpp:199
ErrorCode PushBatch(const Data *data, size_t size)
批量推入数据 / Pushes multiple elements into the queue
ErrorCode PopBatch(Data *data, size_t size)
批量弹出数据 / Pops multiple elements from the queue
原始数据封装类。 A class for encapsulating raw data.
size_t size_
数据大小(字节)。 The size of the data (in bytes).
void * addr_
数据存储地址。 The storage address of the data.
ReadPort class for handling read operations.
Definition libxr_rw.hpp:272
void ProcessPendingReads(bool in_isr)
Processes pending reads.
Definition libxr_rw.cpp:127
通用异步收发传输(UART)基类 / Abstract base class for Universal Asynchronous Receiver-Transmitter (UART)
Definition uart.hpp:19
@ NO_PARITY
无校验 / No parity
@ ODD
奇校验 / Odd parity
@ EVEN
偶校验 / Even parity
WritePort * write_port_
写入端口 / Write port
Definition uart.hpp:54
WritePort class for handling write operations.
Definition libxr_rw.hpp:413
void Finish(bool in_isr, ErrorCode ans, WriteInfoBlock &info)
更新写入操作的状态。 Updates the status of the write operation.
Definition libxr_rw.cpp:191
LibXR 命名空间
Definition ch32_can.hpp:14
ErrorCode(* ReadFun)(ReadPort &port, bool in_isr)
Function pointer type for read operations.
Definition libxr_rw.hpp:249
ErrorCode(* WriteFun)(WritePort &port, bool in_isr)
Function pointer type for write operations.
Definition libxr_rw.hpp:245
UART 配置结构体 / UART configuration structure.
Definition uart.hpp:44
uint8_t stop_bits
停止位长度 / Number of stop bits
Definition uart.hpp:50
Parity parity
校验模式 / Parity mode
Definition uart.hpp:47
uint32_t baudrate
波特率 / Baud rate
Definition uart.hpp:45
ConstRawData data
Data buffer. 数据缓冲区。
Definition libxr_rw.hpp:263